The present invention relates to a semiconductor circuit employing insulated gate field effect transistors (IGFET's ), and more particularly a dynamic type logic circuit which is suitable for a dynamic random access memory.
In general, in a semiconductor circuit employing IGFET's, it is necessary to hold a mode in a high impedance state which is coupled to a capacitor and an IGFET either at "0" level or at "1" level for a long period of time. However, if a leakage source is present within the node, the high impedance node cannot hold the logic information and its level decays gradually. Especially in a dynamic memory of a multi-address system, since the circuit is controlled by two external control signals called RAS (Row Address Strobe) and CAS (Column Address Strobe), if the node of the internal circuit is not refreshed for a long period of time and if it is not provided with means for holding its level, then the node will have its level lowered gradually and eventually it becomes impossible to obtain a normal response. This memory system is described in U.S. Pat. No. 3,969,706 issued to Robert James Proebsting et al.